The present invention relates to a packet-type memory LSI which is provided with one or more built-in on-chip coprocessors (i.e. a coprocessor-integrated packet-type memory LSI), and a packet-type memory/coprocessor bus for connecting the coprocessor-integrated packet-type memory LSIs with the bus master.
Generally, memory LSIs are increasingly required accessibility with wider data bandwidth if storage capacities of the memory LSIs become larger. This will be easily understood by analogy with a bag in which a lot of articles are stored. Suppose the size of a bag is made larger and larger, and meanwhile the size of its opening remains the same, the bag is necessitated to become more and more inconvenient for storing and taking out the articles. Similarly, suppose the storage capacity of a memory LSI is made larger and its data bandwidth remains the same, the memory LSI will become very unusable for writing and reading data. Therefore, it is very important to keep the balance between the storage capacity and the data bandwidth in order to realize a memory LSI which is usable in a system, and thus development for extending the data bandwidth is growingly promoted mainly on DRUMs which are memory LSIs having the largest storage capacity.
In order to extend the data bandwidth, the operating frequency of the interface between the memory LSI and external devices has to be increased as high as possible, in which simultaneous operation of external I/O signal terminals becomes an obstacle. In the case where a plurality of signal terminals are operating simultaneously at high speed, power consumption of the memory LSI chip becomes high and intense switching noise occurs, and thereby operation errors are caused. Further, when the number of external I/O signal terminals is large, timing skews between the external I/O signal terminals tend to occur and timing adjustment becomes difficult, and thus the high speed operation of becomes difficult.
For such reasons, there have been developed some techniques in order to realize the wider data bandwidth of DRAMs. In such techniques, the number of signal lines in a memory bus to which a DRAM is connected is reduced, and the number of terminals in the external I/O signal terminal of a DRAM is reduced, and the operation frequency of the memory bus is increased. Typical examples of such DRAMs are Rambus DRAMs, SLDRAMs (formerly known as SyncLink DRAMs), Mediachannel DRAMs, etc. Detailed description of the Rambus DRAMs are given in a variety of manuals published by Rambus Inc. The SLDRAMs are now on construction of their specifications as standardized techniques in the IEEE by the SLDRAM Consortium (former SyncLink Consortium), and tentative specifications are shown in xe2x80x9cSLDRAM: High-Performance, Open-Standard Memoryxe2x80x9d, IEEE Micro November/December 1997, pp.29-39=l , or xe2x80x9cDraft Standard for A High-Speed Memory Interface (SLDRAM)xe2x80x9d, Draft 099 P1596.7-199x (http://www.sldram.com/Documents/SyncLinkD0xe2x80x9499.pdf). And with regard to the Mediachannel DRAMs, detailed description is given in a paper which has been presented in a well-known international conference COMPCON""96 (Spring): Tim Robinson et al. xe2x80x9cMulti-Gigabyte/sec DRAM with the MicroUnity Mediachannel Interfacexe2x80x9d, Proc. of COMPCON""96 (Spring), pp.378 (1996).
In DRAMs employing such techniques, memory bus techniques or DRAM interface techniques called xe2x80x98packet-typexe2x80x99 or xe2x80x98protocol-typexe2x80x99 are adopted in order to realize effective DRAM access as well as realizing the small number of the signal lines and the small number of terminals in the external I/O signal terminal. Therefore, DRAMs and memory buses according to such conventional techniques will be hereafter referred to as xe2x80x98packet-type DRAMsxe2x80x99 and xe2x80x98packet-type memory busesxe2x80x99, respectively.
In the following, description will be given on the packet-type DRAM and the packet-type memory bus.
FIG. 1 is a block diagram showing an example of composition of a conventional packet-type DRAM 1001. In FIG. 1, the packet-type DRAM 1001 comprises a memory section 11, a control section 1012, and an interface section 13.
The memory section 11 consists of a DRAM core section 15 and a memory control register section 16. The DRAM core section 15 is composed of a plurality of DRAM banks 17 and a plurality of sense amplifiers 18 which are provided corresponding to each of the DRAM banks 17, and the memory control register section 16 includes a plurality of memory control registers 29.
The control section 1012 includes a memory control logic circuit 1019, a control signal register 20, a write data register 21, a read data register 22, and a memory device ID verification circuit 1023. The control section 1012 is provided with three I/O signal terminals to be connected with the interface section 13. The I/O signal terminals of the control section 1012 include a control signal terminal 24 and a write data terminal 25 (input terminals) and a read data terminal 26 (output terminal).
The interface section 13 is connected with an external I/O terminal 5. The memory section 11 and the control section 1012 are connected together by an internal memory data bus 27 which is a bidirectional bus.
FIG. 2A through FIG. 2C are block diagrams showing examples of connections between the conventional packet-type DRAM 1001 and a microprocessor 9 via a packet-type memory bus 1002. Three types of connections are shown in FIG. 2A through FIG. 2C. The packet-type memory bus 1002 is a single bus master type bus and only one bus master is allowed to exist on the packet-type memory bus 1002. All of the packet-type DRAMs 1001 connected to the packet-type memory bus 1002 operate as slave devices. Here, the word xe2x80x98bus masterxe2x80x99 generally means a device which can exclusively control a bus and send requests to the bus, and the word xe2x80x98slave devicexe2x80x99 generally means a device which does not spontaneously send requests to the packet-type memory bus 1002 but only responds to the request from the bus master. As will be explained, by allowing only one bus master on the bus, the bus master can send a request without arbitration for the bus exclusive ownership of the packet-type memory bus 1002, thereby the protocols for the packet-type memory bus 1002 can be simplified. Incidentally, although the microprocessor 9 is provided as the bus master of the packet-type memory bus 1002 in FIG. 2A through FIG. 2C, other type of a bus master can be provided to the packet-type memory bus 1002, such as a memory controller, a signal processor, a graphics accelerator, an ASIC of other type, etc.
In the composition of FIG. 2A, in the same way as the packet-type DRAM 1001 of FIG. 1, the packet-type DRAM 1001 of FIG. 2A is composed of a memory section 11, a control section 1012, and an interface section 13. All of the I/O terminals of the control section 1012, i.e. the control signal terminal 24, the write data terminal 25 and the read data terminal 26, are connected to the interface section 13. The interface section 13 is connected to the packet-type memory bus 1002 via the external I/O terminal 5. The packet-type memory bus 1002 connects the microprocessor 9 and the packet-type DRAMs 1001. The packet-type memory bus 1002 in FIG. 2A is a bidirectional bus.
In the composition of FIG. 2B, the interface section 13 is composed of a control interface section 13-1 and a data interface section 13-2. The control signal terminal 24 of the control section 1012 is connected to the control interface section 13-1, and the write data terminal 25 and the read data terminal 26 of the control section 1012 are connected to the data interface section 13-2. The packet-type memory bus 1002 of FIG. 2B is composed of a control bus 1002-1 and a data bus 1002-2. The control interface section 13-1 is connected to the control bus 1002-1, and the data interface section 13-2 is connected to the data bus 1002-2. In FIG. 2B, the control bus 1002-1 is a unidirectional bus from the microprocessor 9 to the packet-type DRAMs 1001, and the data bus 1002-2 is a bidirectional bus.
In the composition of FIG. 2C, the interface section 13 is composed of a request interface section 13-3 and a response interface section 13-4. The control signal terminal 24 and the write data terminal 25 of the control section 1012 are connected to the request interface section 13-3, and the read data terminal 26 of the control section 1012 is connected to the response interface section 13-4. The packet-type memory bus 1002 of FIG. 2C is composed of a request bus 1002-3 and a response bus 1002-4. The request interface section 13-3 is connected to the request bus 1002-3, and the response interface section 13-4 is connected to the response bus 1002-4. In FIG. 2C, the request bus 1002-3 is a unidirectional bus from the microprocessor 9 to the packet-type DRAMs 1001, and the response bus 1002-4 is a unidirectional bus in the reverse direction.
FIG.3 is a classification table showing process requests which are requested to the packet-type DRAM 1001. Process types include xe2x80x98memory accessxe2x80x99, xe2x80x98initializationxe2x80x99 and xe2x80x98refreshxe2x80x99. Each of the processes is requested by the bus master of the packet-type memory bus 1002, i.e. the microprocessor 9 in FIG. 2A through FIG. 2C. The xe2x80x98memory accessxe2x80x99 process is classified into two types with regard to destinations, i.e. a memory access to the DRAM core section 15 in the memory section 11 and a memory access to the memory control register section 16 in the memory section 11. Each of the memory access to the DRAM core section 15 and the memory access to the memory control register section 16 includes two types of operations (commands), i.e. read and write. Further, in the case of the access to the DRAM core section 15, data length of the read or write data is designated. Generally, the data length is approximately 8 bytes to 256 bytes, for example. In the case of the access to the memory control register section 16, data of a fixed data length is generally read or written, in which the data length is set at the data length of the memory control register 29 of the memory control register section 16 (for example, 8 bytes) or at a shorter fixed data length. The xe2x80x98initializationxe2x80x99 includes operations of resetting the internal states of the memory control logic circuit 1019, storing specific device information of the packet-type DRAM 1001 into the memory control register section 16, etc. The xe2x80x98refreshxe2x80x99 generally means periodic rewriting to DRAM cells, for keeping memory of the DRAM cells which is necessary for the operation of the DRAM.
In the following, DRAM access operations to the packet-type DRAM 1001 will be explained first, referring to FIG. 1 and FIG.3. In any type of DRAM access, the xe2x80x98process typexe2x80x99, the xe2x80x98destinationxe2x80x99, the xe2x80x98operationxe2x80x99, and the xe2x80x98data lengthxe2x80x99 which are shown in FIG. 3 are designated by the microprocessor 9 (i.e. the bus master) and the designated information is transmitted to the control signal terminal 24 of the control section 1012 of the packet-type DRAM 1001, via the external I/O terminal 5 and the interface section 13. The designated information further includes a memory address for designating one of the DRAM banks 17 and a position therein to be made access, or a memory control register number for designating a specific memory control register 29 in the memory control register section 16. Such information supplied via the control signal terminal 24 will hereafter be referred to as xe2x80x98control signal informationxe2x80x99.
The control signal information further includes a memory device ID for selecting one or more packet-type DRAMs 1001 out of a plurality of packet-type DRAMs 1001 which are connected to the packet-type memory bus 1002. Each packet-type DRAM 1001 is provided with a specific memory device ID and the memory device ID is stored in specific one of the memory control registers 29 in the memory control register section 16, and the memory device ID verification circuit 1023 in each packet-type DRAM 1001 verifies the device ID included in the control signal information against the memory device ID of the packet-type DRAM 1001 itself. By the verification, it is judged whether the destination of the request (such as DRAM access) which has been supplied via the external I/O terminal 5 is the packet-type DRAM 1001 itself or not. If the destination of the DRAM access request is not the packet-type DRAM 1001 itself, the following operations will not be executed. Incidentally, there are cases where the device ID included in the control signal information designates memory device IDs of two or more packet-type DRAMs 1001.
In the control section 1012, data which has been read out is outputted from the read data terminal 26 in the case of reading access, and data which should be written is supplied to the write data terminal in the case of writing access. The control signal register 20, the write data register 21, and the read data register 22 operate as I/O latches (or I/O registers) for the control signal terminal 24, the write data terminal 25, and the read data terminal 26, respectively. The memory control logic circuit 1019 determines subsequent operation according to the control signal information which is supplied via the control signal terminal 24 and controls the DRAM access. In the control of the DRAM access, the memory control logic circuit 1019 refers to memory in the memory control registers 29 in the memory control register section 16 when necessary. In the case of DRAM access to the DRAM core section 15, a desired DRAM bank 17 is selected by the designation of the memory address, and data in the DRAM bank 17 is made access via a corresponding sense amplifier 18. Here, the sense amplifier 18 operates also as a cache memory or a high-speed buffer for the corresponding DRAM bank 17. Therefore, when the range of the addresses for the DRAM access is within the data which has already been temporarily stored in the sense amplifier 18, the sense amplifiers 18 instead of the DRAM bank 17 is made access with a high speed, thereby high speed DRAM access is made possible.
In the case of DRAM access to the DRAM core section 15, access to the DRAM bank 17 is executed depending on whether the desired data has already been temporarily stored in the sense amplifier 18 or not, and thus access time widely varies. In the case where the subsequent access is addressed to data which is not temporarily stored in the sense amplifier 18, it is often advantageous for high speed access if the data temporarily stored in the sense amplifier 18 is written back to the DRAM bank 17 before the subsequent access. Therefore, in the case of DRAM access to the DRAM core section 15, the control signal information usually includes information with regard to control of the DRAM core section 15, such as whether access to the DRAM bank 17 should be executed or not, whether data in the sense amplifier 18 should be written back to the DRAM bank 17 or not, etc.
As mentioned above, in the conventional composition of the packet-type memory buses 1002 which have been explained referring to FIG. 2A through FIG. 2C, it is characteristic of the packet-type memory bus 1002 to be composed of a very small number of signal lines. Concretely, the number of the signal lines is approximately 10 to 30. In the conventional techniques, Rambus employs the composition of FIG. 2A, the SLDRAM Consortium employs the composition of FIG. 2B, and Mediachannel employs the composition of FIG. 2C. As mentioned above, in order to send the control signal information, which is necessary for the DRAM access, from the microprocessor 9 to the packet-type DRAMs 1001 via a small number of signal lines, or in order to execute data transmission between the microprocessor 9 and the packet-type DRAMs 1001 using a small number of signal lines, a system for assembling the control signal information and the data into packets and sending/receiving the packets during some cycles is needed to be provided. Further, for assembling and disassembling such packets, some fixed protocols have to be established.
FIGS. 4A and 4B are schematic diagrams showing classification of packets transmitted on the packet-type memory bus 1002. Two kinds of packets shown in FIG. 4A, i.e. the request packet and the write data packet, are transmitted from the microprocessor 9 to the packet-type DRAMs 1001. The request packet is a variable length packet which is generated by encoding the aforementioned control signal information according to predetermined protocols. The write data packet includes write data whose size is variable. Meanwhile, two kinds of packets shown in FIG. 4B, i.e. the read data packet and the acknowledge packet, are transmitted from the packet-type DRAMs 1001. The read data packet includes read data whose size is variable. The acknowledge packet is generally a fixed length packet. The acknowledge packet is necessary in some cases and unnecessary in other cases, as will be explained below.
The acknowledge packet is necessary in the case where the microprocessor 9 (i.e. the bus master), which is making a request for a DRAM access to the packet-type DRAM 1001, can not judge whether or not the packet-type DRAM 1001 can accept the DRAM access request, or whether or not the packet-type DRAM 1001 can immediately respond to the request, for example, in the case where access to the DRAM core section 15 should be requested during the refresh of the packet-type DRAM 1001 and the microprocessor 9 does not know whether or not the refresh is in process. Further, the acknowledge packet is necessary in the case where the microprocessor 9 does not know whether or not data to be made access has already been temporarily stored in the sense amplifier 18. In such cases, the acknowledge packet includes information indicating whether the requested access can be accepted or not, and information instructing the microprocessor 9 how to operate in the case where the requested access can not be accepted. The instruction can be, for example, an instruction to request for access again after a predetermined time, or an instruction to wait for a predetermined time till the access is completed. On the other hand, the acknowledge packet is unnecessary in the case where the microprocessor 9 fully manages and grasps the internal states of the packet-type DRAM 1001 and thus the access is guaranteed to be accepted when the microprocessor 9 makes the access request. Rambus employs a method which needs the acknowledge packet, and the SLDRAM Consortium employs a method which does not need the acknowledge packet.
FIG. 5A through FIG. 5C are schematic diagrams showing transmission of packets on the packet-type memory bus 1002 in each composition of FIG. 2A through FIG. 2C. In FIG. 5A through FIG. 5C, the microprocessor 9 (the bus master) is placed on the left-hand side, and the packet-type DRAMs 1001 (the slave devices) are placed on the right-hand side, in the same way as FIG. 2A through FIG. 2C.
In the composition of FIG. 2A, every type of packets are transmitted on one bidirectional packet-type memory bus 1002. Therefore, the packet transmission in FIG. 5A is shown classified with respect to two operations: writing and reading. In the writing operation, the microprocessor 9 sends a request packet first, and then sends a write data packet. To this, the packet-type DRAM 1001 sends an acknowledge packet, and then the write data is correctly written if accepted. In the reading operation, the microprocessor 9 sends a request packet and the packet-type DRAM 1001 sends an acknowledge packet. If accepted, the packet-type DRAM 1001 subsequently sends a read data packet. Incidentally, as mentioned above, above operations without using the acknowledge packets are also possible, in which transmission of other kinds of packets are the same as FIG. 5A.
FIG. 5B is showing which packet is transmitted on the control bus 1002-1 or the data bus 1002-2 in the composition of FIG. 2B. The request packet is transmitted on the control bus 1002-1, and the write data packet, the read data packet and the acknowledge packet are transmitted on the data bus 1002-2. As mentioned above, there are cases where the acknowledge packet is not used, and the SLDRAM Consortium which adopts this type of composition does not actually use the acknowledge packet.
FIG. 5C is showing which packet is transmitted on the request bus 1002-3 or the response bus 1002-4 in the composition of FIG. 2C. The request packet and the write data packet are transmitted on the request bus 1002-3, and the read data packet and the acknowledge packet are transmitted on the response bus 1002-4. As mentioned above, there are cases where the acknowledge packet is not used.
FIG. 6A and FIG. 6B are flow charts showing the operation of the packet-type DRAM 1001 when a request packet is received. FIG. 6A is showing the case where the acknowledge packet is necessary, and FIG. 6B is showing the case where the acknowledge packet is unnecessary. Referring to FIG. 6A, when the request packet is received, the packet-type DRAM 1001 verifies the memory device ID and judges whether it has to respond to the request or not. If the memory device ID was not the memory device ID of the packet-type DRAM 1001 itself, the process is ended. If the memory device ID matched, the packet-type DRAM 1001 disassembles the request packet and determines access mode. Subsequently, the packet-type DRAM 1001 judges whether or not the packet-type DRAM 1001 can correctly respond to the request for the access to the DRAM core section 15 or the memory control register section 16 according to the determined access mode. Subsequently, the packet-type DRAM 1001 assembles an acknowledge packet according to the result of the judgment etc. and sends the acknowledge packet. The acknowledge packet includes information indicating whether the packet-type DRAM 1001 accepts the request or not. When the request is accepted, the access is executed. In the case of reading access, the packet-type DRAM 1001 sends a read data packet and the process is ended. In the case of writing access, the packet-type DRAM 1001 receives a write data packet and the write data is written in the DRAM core section 15 or the memory control register section 16, and the process is ended. When the request is not accepted, the packet-type DRAM 1001 executes access preparation. Here, the access preparation includes waiting for completion of a refresh if during the refresh, or transferring data from the DRAM bank 17 to the sense amplifier 18 if the address of the requested data does not correspond to the address of the data which has been temporarily stored in the sense amplifier 18. After the access preparation, the packet-type DRAM 1001 shifts into access operation and operates in the same way as the case where the request is accepted, or finishes the operation with regard to the particular request packet and waits for another reception of a request packet.
In FIG. 6B, the operation of the packet-type DRAM 1001 is rather simpler since the acknowledge packet is not used. After the verification of the memory device ID, the request packet is disassembled and access mode is determined, the reading or writing access is executed, and the operation with regard to the request packet is ended.
FIG. 7A through FIG. 7E are schematic diagrams showing typical packet formats of each packet, taking the technique of the SLDRAM Consortium as an example. FIG. 7A through FIG. 7C are showing examples of request packets, and FIG. 7D is showing an example of an acknowledge packet, and FIG. 7E is showing an example of a read data packet or a write data packet. Incidentally, in the technique of the SLDRAM Consortium, the control bus 1002-1 is composed of 10-bit memory bus signal lines and the data bus 1002-2 is composed of 16-bit memory bus signal lines.
FIG. 7A is showing a request packet for requesting writing access or reading access to the DRAM core section 15. The request packet of FIG. 22A occupies the 10-bit control bus 1002-1 during four cycles. In the first cycle, the first 7 bits are used as a device ID field for designating the device ID, and the remaining 3 bits are used as a command field for designating a command No.0. In the second cycle, the first 3 bits are used as a command field for designating a command No.1, and the remaining 7 bits are used as a parameter field for designating a parameter No.0. The remaining two cycles are used as parameter fields for designating parameters No.1 and No.2 respectively. The control signal information which has been explained referring to FIG. 3, including the process type, the destination, the operation, the data length, the information about the control of the DRAM core section 15, etc., is designated in the command fields for the command No.0 and the command No.1. Addresses of data in the DRAM core section 15 are designated in the parameter fields for the parameter No.0, the parameter No.1 and the parameter No.2.
FIG. 7B is showing a request packet for requesting reading access to the memory control register section 16. One of the memory control registers 29 in the memory control register section 16 to be made access is designated in the parameter No.0 field in the latter 7 bits of the second cycle.
FIG. 7C is showing a request packet for requesting writing access to the memory control register section 16. One of the memory control registers 29 in the memory control register section 16 to be made access is designated in the parameter No.0 field in the latter 7 bits of the second cycle. The write data is designated in the parameter No.1 field in the third cycle and the parameter No.2 field in the fourth cycle.
As shown in FIG. 7A through FIG. 7C, the device ID field is included in every request packet, and which of the packet-type DRAMs 1001 has to respond to the request is uniquely determined by the verification against the device ID field. Similarly, the fields for the command No.0 and the command No.1 are common to every request packet, and the access operation to be executed in the packet-type DRAM 1001 is uniquely determined by decoding the fields. The parameter fields are used for designation of the address of data in the DRAM core section 15, the memory control register 29, the write data, etc., depending on the type of the requested access. Incidentally, the designation by the device ID field is not limited to one packet-type DRAM 1001, and there are cases where a plurality of packet-type DRAMs 1001 are designated at once (referred to as xe2x80x98multicastxe2x80x99), or cases where all the packet-type DRAMs 1001 connected to the packet-type memory bus 1002 are designated at once (referred to as xe2x80x98broadcastxe2x80x99).
FIG. 7D is showing an example of a packet format of an acknowledge packet. Actually, the acknowledge packet does not exist in the technique of the SLDRAM Consortium, and thus FIG. 7D is showing a format of an acknowledge packet of Rambus which is realized on the SLDRAM data bus 1002-2. The acknowledge packet of FIG. 7D occupies the data bus 1002-2 during one cycle, in which the first 2 bits are used to indicate whether the request can be accepted or not (i.e. whether response to the request can be executed or not), or whether some system error exists or not.
FIG. 7E is showing an example of a format of a write data packet or a read data packet. Each of the write data packet and the read data packet transmits variable length data, occupying the data bus 1002-2 during a necessary number of cycles.
As described above, the packet-type DRAM 1001 and the packet-type memory bus 1002 in the conventional techniques realize functions for transmitting packets between the bus master and the packet-type DRAMs 1001 based on predetermined protocols. Meanwhile, in the fields of parallel processing systems and distributed processing systems, conventional techniques for communicating between a plurality of devices have long been used. In such systems, a plurality of devices (or nodes) are connected via buses or a network, and packet transmission or other kinds of communication means are used in order to execute mutual process request between the devices (nodes) or in order to synchronize parallelly executed processes.
A variety of such conventional techniques exist, in which the xe2x80x98processor busxe2x80x99 for the Pentium Pro microprocessor of Intel can be taken as an example. Description of the processor bus is given in a paper which has been presented in the international conference COMPCON""96 (Spring): Nitin Sarangdhar et al. xe2x80x9cAn Overview of the Pentium Pro Processor Busxe2x80x9d, Proc. of COMPCON""96 (Spring), pp.383 (1996). The Pentium Pro processor bus has been designed on the assumption of connecting a plurality of Pentium Pro microprocessors, memory controllers, I/O controllers, etc., and methods for physical and electrical connection of the devices and driving protocols for the processor bus have been established. Further, standard method for maintaining cache coherency between a plurality of Pentium Pro microprocessors has been established for the Pentium Pro processor bus. Here, the xe2x80x98cache coherencyxe2x80x99 means a state in which copies, which have been respectively stored in cache memories of each node by copying from the same data, have the same value.
As mentioned above, the conventional techniques using the packet-type DRAM 1001 and the packet-type memory bus 1002 realize functions for transmitting packets according to predetermined protocols. In such conventional techniques, the functions for packet transmission are utilized only for the DRAM access to the packet-type DRAMs 1001, i.e. for the reading access or the writing access to the DRAM core section or the memory control register section 16 and for the control of the initialization or the refresh of the packet-type DRAM 1001. However, the original applicability of such functions realizing communication by packet transmission does not have to be limited to such DRAM access. In other words, such functions can be utilized as communication means which can meet various types of purposes.
As an example of such purposes, one or more coprocessors provided with functions for some arithmetic logic operation may be built in the packet-type DRAM 1001, and the arithmetic logic operation of the coprocessors may be controlled by the bus master by sending some type of packet from the bus master via the packet-type memory bus 1002. In such a packet-type DRAM provided with built-in coprocessors (i.e. a coprocessor-integrated packet-type DRAM), internal access with wide bandwidth and low latency can be executed to the on-chip DRAM, and thus the built-in coprocessors can execute effective arithmetic logic operation by the internal access to data stored in the bulk storage on-chip DRAM with wide bandwidth and low latency. As explained above, no consideration has been given to the other purposes (than the DRAM access) of the packet transmission functions of the conventional techniques using the packet-type DRAM 1001, and thus the conventional techniques is not sufficient as a memory bus technique for controlling the aforementioned coprocessor-integrated packet-type DRAM.
Meanwhile, it seems that such external control of the arithmetic logic operation of the coprocessor which is built in the DRAM (i.e. external control of the on-chip coprocessor) can be easily realized by applying the aforementioned other techniques such as the processor buses in parallel processing systems etc. However, such problem solving involves the following drawbacks.
The protocols for the processor bus etc. in parallel processing systems are rather more complex than the protocols for the packet-type memory bus 1002 for some reasons. First, the processor bus has been designed on the assumption of a plurality of bus masters. There are cases where a plurality of bus masters make requests to the processor bus at once, and thus the arbitration for the bus exclusive ownership of the processor bus has to be executed between the bus masters. Further, flow control is necessary on the processor bus in order to avoid deadlock or livelock. Further, the protocols have to provide support for a variety of communication formats (packet formats) on many kinds of buses and a variety of communication patterns (i.e. between which devices communication should be executed, with what timing transmission should be executed, etc.) on many kinds of buses. Furthermore, specifications for guaranteeing data consistency such as the cache coherency between a plurality of processors may have to be included in the protocols. In this way, the protocols for the processor bus are very complex, therefore communication in such systems via processor buses takes much longer time.
On the other hand, the protocols for the packet-type memory bus 1002 can be rather similar, since the bus master to make requests to the packet-type memory bus 1002 is only one and the arbitration for the bus exclusive ownership is not necessary, and since the protocols are not needed to provide support for many kinds of packet formats. Further, if the bus master such as a microprocessor, a memory controller, etc. of the packet-type memory bus 1002 is designed to manage and grasp the internal states of the packet-type DRAMs 1001, protocols can be constructed without the use of the acknowledge packet as mentioned above, therefore very simple protocols can be realized. Therefore, the conventional systems with simple protocols using the packet-type DRAM 1001 and the packet-type memory bus 1002 have strong points in that assembling, transmission and disassembling of packets can be executed with higher speed, and communication via the packet-type memory bus 1002 can be executed in a short time. Reduction of the DRAM access time along with the extension of data bandwidth is a main challenge in designing of DRAMs. Therefore, the above characteristics are very advantageous for memory buses which are used for constructing DRAM systems.
To sum up, if a system with the packet-type DRAM 1001 and the packet-type memory bus 1002 is tried to be constructed employing the conventional techniques in the fields of parallel processing systems or distributed processing systems, processing of protocols requires much time and the DRAM access time is necessitated to be considerably increased. When it is attempted to realize the aforementioned coprocessor-integrated packet-type DRAM which can be made external reading access and writing access as a general packet-type DRAM 1001, it is not allowed if the access time of the packet-type DRAM 1001 itself increases in order to realize the external control of the arithmetic logic operation functions of the built-in coprocessor. On the other hand, the external control of the arithmetic logic operation functions of the on-chip built-in coprocessor can not be realized by the conventional packet-type DRAM 1001 and the packet-type memory bus 1002.
It is therefore the primary object of the present invention to provide a flexible and high-performance packet-type DRAM with built-in coprocessors (i.e. a coprocessor-integrated packet-type DRAM), with which external control of the arithmetic logic operation functions of the on-chip built-in coprocessor can be realized.
Another object of the present invention is to provide such a coprocessor-integrated packet-type DRAM, needing no spatial/temporal overhead with respect to both the number of terminals in the external I/O signal terminal and the DRAM access time to the on-chip packet-type DRAM itself, in comparison with the conventional packet-type DRAM.
Another object of the present invention is to provide a packet-type memory/coprocessor bus which can realize external control of the coprocessor-integrated packet-type DRAM, with which both the external control of the arithmetic logic operation functions of the on-chip built-in coprocessor and the DRAM access to the packet-type DRAM on the same chip are realized.
Another object of the present invention is to provide such a packet-type memory/coprocessor bus, needing no spatial/temporal overhead with respect to both the number of the signal lines composing the bus and bus timing on the DRAM access, in comparison with the conventional packet-type memory bus.
Another object of the present invention is to provide a coprocessor-integrated packet-type DRAM and a packet-type memory/coprocessor bus, by which an arbitrary number of the packet-type DRAMs and an arbitrary number of the coprocessor-integrated packet-type DRAMs can be connected in a mixed arrangement to the same packet-type memory/coprocessor bus, in which the DRAM access to the packet-type DRAMs, the DRAM access to the coprocessor-integrated packet-type DRAMs, and the control of the arithmetic logic operation functions of the on-chip built-in coprocessors in the coprocessor-integrated packet-type DRAMs can be executed via the packet-type memory/coprocessor bus.
In accordance with a 1st aspect of the present invention, there is provided a coprocessor-integrated packet-type memory LSI to be connected to a packet-type memory/coprocessor bus out of the coprocessor-integrated packet-type memory LSI via an external I/O terminal having a desired number of signal terminals, comprising a memory section, a control section, an interface section, and a desired number of coprocessor sections. In the coprocessor-integrated packet-type memory LSI, a memory device ID and coprocessor device IDs are assigned to the memory section and the coprocessor sections respectively and are stored in the coprocessor-integrated packet-type memory LSI, in which the memory device ID and the coprocessor device IDs are assigned so that each of them can uniquely designate one memory section or one coprocessor section out of all of the memory sections and the coprocessor sections in all of the coprocessor-integrated packet-type memory LSIs which are connected to the packet-type memory/coprocessor bus.
In accordance with a 2nd aspect of the present invention, in the 1st aspect, the memory section includes a memory core section and a memory control register section including a desired number of memory control registers. The coprocessor section includes an operation core section, an operation control section, and an operation control register section including a desired number of operation control registers. The control section and the memory section are connected by an internal memory data bus, and the control section and the coprocessor sections are connected by internal coprocessor data buses.
In accordance with a 3rd aspect of the present invention, in the 2nd aspect, the memory core section is composed of dynamic random access memory.
In accordance with a 4th aspect of the present invention, there is provided a packet-type memory/coprocessor bus for connecting a bus master and a desired number of coprocessor-integrated packet-type memory LSIs of the 1st, 2nd or 3rd aspect. The packet-type memory/coprocessor bus is a single bus master type bus needing no arbitration for its bus exclusive ownership to be executed by the bus master when the bus master transmits a packet to the packet-type memory/coprocessor bus, in which two types of packets including a request packet and a write data packet can be transmitted by the bus master to the packet-type memory/coprocessor bus, and a read data packet can be transmitted by the coprocessor-integrated packet-type memory LSI to the packet-type memory/coprocessor bus.
In accordance with a 5th aspect of the present invention, there is provided a packet-type memory/coprocessor bus for connecting a bus master and a desired number of coprocessor-integrated packet-type memory LSIs of the 1st, 2nd or 3rd aspect. The packet-type memory/coprocessor bus is a single bus master type bus needing no arbitration for its bus exclusive ownership to be executed by the bus master when the bus master transmits a packet to the packet-type memory/coprocessor bus, in which two types of packets including a request packet and a write data packet can be transmitted by the bus master to the packet-type memory/coprocessor bus, and two types of packets including a read data packet and an acknowledge packet can be transmitted by the coprocessor-integrated packet-type memory LSI to the packet-type memory/coprocessor bus.
In accordance with 6th and 7th aspects of the present invention, in the 4th and 5th aspects, the request packet includes a device ID field for designating the destination of the request packet out of all of the memory sections and the coprocessor sections in all of the coprocessor-integrated packet-type memory LSIs which are connected to the packet-type memory/coprocessor bus, a command field for designating a process which the request packet requests, and a parameter filed for designating parameters which are necessary for the execution of the process which is requested by the request packet.
In accordance with 8th and 9th aspects of the present invention, in the 6th and 7th aspects, the device ID field has a fixed field length regardless of whether the device ID field designates a memory section or a coprocessor section, and the command field also has a fixed field length regardless of whether the device ID field designates a memory section or a coprocessor section.
In accordance with 10th and 11th aspects of the present invention, in the 6th and 7th aspects, the device ID field has a fixed field length regardless of whether the device ID field designates a memory section or a coprocessor section, and the field length of the command field varies depending on whether the device ID field designates a memory section or a coprocessor section.
In accordance with 12th, 13th, 14th and 15th aspects of the present invention, in the 8th, 9th, 10th and 11th aspects, the packet-type memory/coprocessor bus includes a control bus which is a unidirectional bus from the bus master to the coprocessor-integrated packet-type memory LSI, and a data bus which is a bidirectional bus between the bus master and the coprocessor-integrated packet-type memory LSI.
In accordance with 16th, 17th, 18th and 19th aspects of the present invention, in the 8th, 9th, 10th and 11th aspects, the packet-type memory/coprocessor bus includes a request bus which is a unidirectional bus from the bus master to the coprocessor-integrated packet-type memory LSI, and a response bus which is a unidirectional bus from the coprocessor-integrated packet-type memory LSI to the bus master.
In accordance with a 20th aspect of the present invention, there is provided a method for controlling the coprocessor-integrated packet-type memory LSI of the 1st, 2nd or 3rd aspect. The method comprises a reception step, a verification step, a decoding step, and an instruction step. In the reception step, the interface section receives the request packet from the packet-type memory/coprocessor bus of the 6th or 7th aspect via the external I/O terminal. In the verification step, the control section verifies the device ID field in the request packet against the memory device ID and the coprocessor device IDs stored in the coprocessor-integrated packet-type memory LSI. In the decoding step, the control section decodes the command field in the request packet, only in the case where the device ID field designates any of the memory device ID and the coprocessor device IDs stored in the coprocessor-integrated packet-type memory LSI. And in the instruction step, the control section instructs the memory section or the coprocessor section designated by the device ID field to execute the process which is requested by the request packet.
In accordance with 21st, 22nd and 23rd aspects of the present invention, in the 1st, 2nd and 3rd aspects, the coprocessor-integrated packet-type memory LSI is controlled by the method of the 20th aspect, and the coprocessor-integrated packet-type memory LSI further comprises a memory device ID register, one or more coprocessor device ID registers, and a memory/coprocessor device ID verification circuit. The memory device ID register stores the memory device ID of the memory section. The coprocessor device ID registers store the coprocessor device IDs of the coprocessor sections respectively. The memory/coprocessor device ID verification circuit is connected with the memory device ID register and the coprocessor device ID registers, and parallelly executes the verification of the device ID field in the request packet against the memory device ID stored in the memory device ID register and the verification of the device ID field in the request packet against the coprocessor device IDs stored in the coprocessor device ID registers respectively, and thereby judges whether or not the device ID field designates each of the memory section and the coprocessor sections in the coprocessor-integrated packet-type memory LSI.
In accordance with a 24th aspect of the present invention, in the 22nd aspect, the memory device ID register is provided as one of the memory control registers in the memory control register section of the memory section, and the coprocessor device ID register is provided as one of the operation control registers in the operation control register section of the coprocessor section.
In accordance with a 25th aspect of the present invention, in the 20th aspect, in the decoding step, the control section employs different decoding methods for decoding the command field depending on whether the device ID field of the request packet designates a memory section or a coprocessor section. Therefore, a command field with a particular bit pattern can designate different process requests depending on whether the device ID field designates a memory section or a coprocessor section.
In accordance with a 26th aspect of the present invention, in the 20th aspect, in the case where the device ID field in the request packet designated the memory section, the control section decodes the command field of the request packet, and instructs the memory section to execute writing access or reading access to the memory core section or the memory control register section in the memory section according to the result of the decoding.
In accordance with a 27th aspect of the present invention, in the 20th aspect, in the case where the device ID field in the request packet designated the memory section, the control section decodes the command field of the request packet, judges whether the memory section can execute writing access or reading access requested by the request packet or not according to the result of the decoding, transmits the judgment result to the packet-type memory/coprocessor bus as the acknowledge packet, and instructs the memory section to execute the writing access or the reading access to the memory core section or the memory control register section in the memory section if the memory section has been judged to be able to execute the access.
In accordance with a 28th aspect of the present invention, in the 20th aspect, in the case where the device ID field in the request packet designated one of the coprocessor sections, the control section decodes the command field of the request packet, and instructs the designated coprocessor section to execute writing access or reading access to the operation control register section in the coprocessor section according to the result of the decoding.
In accordance with a 29th aspect of the present invention, in the 20th aspect, in the case where the device ID field in the request packet designated one of the coprocessor sections, the control section decodes the command field of the request packet, judges whether the designated coprocessor section can execute writing access or reading access requested by the request packet or not according to the result of the decoding, transmits the judgment result to the packet-type memory/coprocessor bus as the acknowledge packet, and instructs the designated coprocessor section to execute the writing access or the reading access to the operation control register section in the coprocessor section if the coprocessor section has been judged to be able to execute the access.
In accordance with a 30th aspect of the present invention, in the 20th aspect, in the case where the device ID field in the request packet designated the memory section, the control section decodes the command field of the request packet, and instructs the memory section to execute writing access or reading access to the memory core section or the memory control register section in the memory section according to the result of the decoding. In the case where the device ID field in the request packet designated one of the coprocessor sections, the control section decodes the command field of the request packet, judges whether the designated coprocessor section can execute writing access or reading access requested by the request packet or not according to the result of the decoding, transmits the judgment result to the packet-type memory/coprocessor bus as the acknowledge packet, and instructs the designated coprocessor section to execute the writing access or the reading access to the operation control register section in the coprocessor section if the coprocessor section has been judged to be able to execute the access.
In accordance with a 31st aspect of the present invention, in the 20th aspect, in the case where the device ID field in the request packet designated the memory section, the control section decodes the command field of the request packet, and instructs the memory section to execute writing access or reading access to the memory core section or the memory control register section in the memory section according to the result of the decoding. In the case where the device ID field in the request packet designated one of the coprocessor sections, the control section decodes the command field of the request packet. Then, if the decoded command field instructed writing access to the operation control register section, the control section judges whether the designated coprocessor section can execute the writing access or not, transmits the judgment result to the packet-type memory/coprocessor bus as the acknowledge packet, and instructs the designated coprocessor section to execute the writing access to the operation control register section in the coprocessor section if the coprocessor section has been judged to be able to execute the access. If the decoded command field instructed reading access to the operation control register section, the control section instructs the designated coprocessor section to execute the reading access to the operation control register section in the coprocessor section.
In accordance with 32nd, 33rd, 34th and 35th aspects of the present invention, in the 26th, 27th, 30th and 31st aspects, in the execution of the writing access to the memory core section, the memory section receives write data which has been included in the write data packet which the control section received from the packet-type memory/coprocessor bus via the interface section, and writes the write data into the memory core section using a memory address which is designated by the parameter field of the request packet.
In accordance with 36th, 37th, 38th and 39th aspects of the present invention, in the 26th, 27th, 30th and 31st aspects, in the execution of the writing access to the memory control register section, the memory section receives write data which has been included in the write data packet which the control section received from the packet-type memory/coprocessor bus via the interface section, and writes the write data into the memory control register which is designated by the parameter field of the request packet.
In accordance with 40th, 41st, 42nd and 43rd aspects of the present invention, in the 26th, 27th, 30th and 31st aspects, in the execution of the writing access to the memory control register section, the memory section receives write data which has been included in part of the parameter field of the request packet from the control section, and writes the write data into the memory control register which is designated by part of the parameter field of the request packet.
In accordance with 44th, 45th, 46th and 47th aspects of the present invention, in the 26th, 27th, 30th and 31st aspects, in the execution of the reading access to the memory core section or the memory control register section, the memory section reads data out of the memory core section or the memory control register section according to the designation by the parameter field in the request packet and supplies the data to the control section, and the control section assembles the read data packet including the data, and the interface section transmits the read data packet to the packet-type memory/coprocessor bus via the external I/O terminal.
In accordance with 48th, 49th, 50th and 51st aspects of the present invention, in the 28th, 29th, 30th and 31st aspects, in the execution of the writing access to the operation control register section, the coprocessor section receives write data which has been included in the write data packet which the control section received from the packet-type memory/coprocessor bus via the interface section, and writes the write data into the operation control register which is designated by the parameter field of the request packet.
In accordance with 52nd, 53rd, 54th and 55th aspects of the present invention, in the 28th, 29th, 30th and 31st aspects, in the execution of the writing access to the operation control register section, the coprocessor section receives write data which has been included in part of the parameter field of the request packet from the control section, and writes the write data into the operation control register which is designated by part of the parameter field of the request packet.
In accordance with 56th, 57th, 58th and 59th aspects of the present invention, in the 28th, 29th, 30th and 31st aspects, in the execution of the reading access to the operation control register section, the coprocessor section reads data out of the operation control register which is designated by the parameter field of the request packet and supplies the data to the control section, and the control section assembles the read data packet including the data, and the interface section transmits the read data packet to the packet-type memory/coprocessor bus via the external I/O terminal.
In accordance with a 60th aspect of the present invention, in the 31st aspect, in the reading access to the memory core section, the memory control register section or the operation control register section, the coprocessor-integrated packet-type memory LSI transmits the read data packet to the packet-type memory/coprocessor bus with predetermined bus timing after the reception of the request packet, and in the writing access to the operation control register section, the coprocessor-integrated packet-type memory LSI transmits the acknowledge packet to the packet-type memory/coprocessor bus with the same predetermined bus timing after the reception of the request packet.
In accordance with 61st, 62nd, 63rd and 64th aspects of the present invention, in the 28th, 29th, 30th and 31st aspects, an operation start register is provided in the operation control register section so that the coprocessor section can refer to the operation start register when the coprocessor section starts execution of an arithmetic logic operation. In the case where writing access to the operation start register is designated by the command field and the parameter field in the request packet, write data included in the parameter field of the request packet or write data included in the write data packet is used as a program pointer indicating an address of the first instruction in an arithmetic logic operation program to be executed, and the coprocessor section starts the execution of the arithmetic logic operation using the program pointer when the program pointer is written into the operation start register.
In accordance with 65th, 66th, 67th and 68th aspects of the present invention, in the 61st, 62nd, 63rd and 64th aspects, in the case where writing access to the operation start register is designated by the request packet, information indicating whether the coprocessor section can execute the designated arithmetic logic operation or not is transmitted as the acknowledge packet to the packet-type memory/coprocessor bus and the arithmetic logic operation is executed by the coprocessor section only when the execution of the designated arithmetic logic operation by the coprocessor section is possible.
In accordance with 69th, 70th, 71st and 72nd aspects of the present invention, in the 56th, 57th, 58th and 59th aspects, an operation result register is provided as one of the operation control registers so that the coprocessor section can write the result of an arithmetic logic operation into the operation result register. In the case where reading access to the operation result register is designated by the command field and the parameter field in the request packet, data stored in the operation result register is read out and assembled as the read data packet and the read data packet is transmitted to the packet-type memory/coprocessor bus.
In accordance with 73rd, 74th, 75th and 76th aspects of the present invention, in the 69th, 70th, 71st and 72nd aspects, in the case where reading access to the operation result register is designated by the request packet, information indicating whether the result of the arithmetic logic operation has already been written in the designated operation result register or not is transmitted as the acknowledge packet to the packet-type memory/coprocessor bus and the reading access to the operation result register is executed only when the result of the arithmetic logic operation has already been written in the operation result register.
In accordance with 77th, 78th, 79th and 80th aspects of the present invention, in the 69th, 70th, 71st and 72nd aspects, in the case where reading access to the operation result register is designated by the request packet, information indicating whether the result of the arithmetic logic operation has already been written in the designated operation result register or not is transmitted included in the read data packet to the packet-type memory/coprocessor bus.
In accordance with 81st, 82nd, 83rd and 84th aspects of the present invention, in the 61st, 62nd, 63rd and 64th aspects, the coprocessor section starts the execution of the arithmetic logic operation according to the writing access to the operation start register, after parameters which are needed by the coprocessor section for executing the arithmetic logic operation have been written into a desired number of the operation control registers by means of the writing access to the operation control registers. Then, the coprocessor section carries out the arithmetic logic operation referring to the parameters stored in the operation control registers.
In accordance with 85th, 86th, 87th and 88th aspects of the present invention, in the 69th, 70th, 71st and 72nd aspects, a desired number of the operation control registers are also used for storing part of the result of the arithmetic logic operation when the result can not be accommodated in the operation result register. The result of the arithmetic logic operation is read out from the coprocessor section by means of reading access to the operation control registers after part of the result is successfully read out by means of the reading access to the operation result register.
In accordance with 89th, 90th, 91st and 92nd aspects of the present invention, in the 56th, 57th, 58th and 59th aspects, a desired number of the operation control registers are used for storing intermediate data which are generated during execution of an arithmetic logic operation by the coprocessor section. In the case where reading access to one of the operation control registers storing the intermediate data is designated by the command field and the parameter field in the request packet, the intermediate data stored in the operation control register is read out and assembled as the read data packet and the read data packet is transmitted to the packet-type memory/coprocessor bus.
In accordance with a 93rd aspect of the present invention, in the 21st aspect, the coprocessor-integrated packet-type memory LSI is provided with an external select-in terminal and an external select-out terminal and each of the memory section and the coprocessor sections is provided with an internal select-in terminal and an internal select-out terminal. A memory section/coprocessor section chain is formed by connecting the internal select-out terminals with corresponding internal select-in terminals and connecting all of the memory section and the coprocessor sections into a chain. The external select-in terminal of the coprocessor-integrated packet-type memory LSI is connected to the internal select-in terminal of the first block of the memory section/coprocessor section chain. And the internal select-out terminal of the final block of the memory section/coprocessor section chain is connected to the external select-out terminal of the coprocessor-integrated packet-type memory LSI.
In accordance with a 94th aspect of the present invention, there is provided a method for controlling the coprocessor-integrated packet-type memory LSI of the 93rd aspect. In the method, as an initialization process, the memory device ID and the coprocessor device IDs of the memory section and the coprocessor sections in the coprocessor-integrated packet-type memory LSI are set at a predetermined initial value and all of the internal select-out terminals of the memory section and the coprocessor sections are set at the logical value xe2x80x980xe2x80x99. After the initialization process, each of the memory section and the coprocessor sections whose memory device ID and the coprocessor device IDs have been set at the initial value ignores writing access thereto and keeps on outputting the logical value xe2x80x980xe2x80x99 from its internal select-out terminal as long as the logical values xe2x80x980xe2x80x99 is supplied to its internal select-in terminal. Each of the memory section and the coprocessor sections accepts the writing access thereto and outputs the logical value xe2x80x981xe2x80x99 from its internal select-out terminal as long as the logical value xe2x80x981xe2x80x99 is supplied to its internal select-in terminal, and thereby the memory device ID or the coprocessor device ID designated by the parameter field of the request packet is written into the memory device ID register or the coprocessor device ID register thereof according to the writing access thereto.
In accordance with 95th and 96th aspects of the present invention, in the 4th and 5th aspects, a coprocessor-integrated packet-type memory LSI chain is formed by connecting a desired number of the coprocessor-integrated packet-type memory LSIs of the 93rd aspect into a chain by connecting the external select-out terminals and corresponding external select-in terminals. The bus master is provided with an external select-in terminal and an external select-out terminal. The external select-out terminal of the bus master is connected to the external select-in terminal of the first coprocessor-integrated packet-type memory LSI in the coprocessor-integrated packet-type memory LSI chain, and the external select-out terminal of the final coprocessor-integrated packet-type memory LSI in the coprocessor-integrated packet-type memory LSI chain is connected to the external select-in terminal of the bus master.
In accordance with a 97th aspect of the present invention, there is provided a method for controlling the packet-type memory/coprocessor bus of the 95th or 96th aspect. In the method, as an initialization process, the memory device IDs and the coprocessor device IDs of all of the memory sections and the coprocessor sections in all of the coprocessor-integrated packet-type memory LSI connected to the packet-type memory/coprocessor bus are set at a predetermined initial value and all of the internal select-out terminals of the memory sections and the coprocessor sections are set at the logical value xe2x80x980xe2x80x99. After the initialization process, the bus master varies the logical value of its external select-out terminal from xe2x80x980xe2x80x99 to xe2x80x981xe2x80x99 and transmits a request packet designating the initial value in the device ID field of the request packet and designating a new memory device ID or a new coprocessor device ID in the parameter field of the request packet, thereby the new memory device ID or the new coprocessor device ID is assigned to the first block in the memory section/coprocessor section chain in the first coprocessor-integrated packet-type memory LSI in the coprocessor-integrated packet-type memory LSI chain. After this, the bus master repeats transmitting request packets designating the initial value in the device ID field of the request packet and designating a new memory device ID or a new coprocessor device ID in the parameter field of the request packet, thereby specific and unique memory device IDs and coprocessor device IDs are assigned to the memory sections and the coprocessor sections in the coprocessor-integrated packet-type memory LSI chain one after another according to the transmission of the logical value xe2x80x981xe2x80x99 through the blocks in the coprocessor-integrated packet-type memory LSI chain.
In accordance with a 98th aspect of the present invention, in the 2nd aspect, the memory section includes a device definition register as one of the memory control registers, for prestoring device definition information to be used for discriminating between a memory section and a coprocessor section, and each of the coprocessor sections includes a device definition register as one of the operation control registers, for prestoring device definition information to be used for discriminating between a memory section and a coprocessor section.
In accordance with a 99th aspect of the present invention, there is provided a method for controlling the coprocessor-integrated packet-type memory LSI of the 98th aspect. In the method, the bus master checks whether a particular device ID has been assigned to a memory section or a coprocessor section, by obtaining the device definition information by executing reading access designating the particular device ID to the device definition register in the memory control register section or the operation control register section.
In accordance with a 100th aspect of the present invention, in the 99th aspect, request packets which are the same except for designation of the device ID field are used by the bus master for the reading accesses to the device definition registers, regardless of whether the destination of the reading access is in a memory section or in a coprocessor section.
In accordance with a 101st aspect of the present invention, in the 2nd aspect, the operation control register section includes a function definition register as one of the operation control registers. The function definition register prestores function definition code which classifies the arithmetic logic operation functions of the coprocessor section.
In accordance with a 102nd aspect of the present invention, there is provided a method for controlling the coprocessor-integrated packet-type memory LSI of the 101st aspect. In the method, the bus master checks arithmetic logic operation functions of a coprocessor section which corresponds to a particular device ID, by obtaining the function definition code by executing reading access designating the particular device ID to the function definition register in the operation control register section.